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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This header file contains identifiers and register-level core functions (or macros) that can be used to access the Xilinx SDI TX core. </p>
<p>For more information about the operation of this core see the hardware specification and documentation in the higher level driver <a class="el" href="xv__sditx_8h.html">xv_sditx.h</a> file.</p>
<pre>
  MODIFICATION HISTORY:</pre><pre>  Ver   Who    Date     Changes
</p>
<hr/>
<p>
  1.0   jsr    07/17/17 Initial release.
</p>
<h1>2.0   vve    10/03/18 Add support for ST352 in C Stream</h1>
</pre><pre>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a612711f22572fe8a9b8622ccab1bac10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sditx__hw_8h.html#a612711f22572fe8a9b8622ccab1bac10">XV_SDITX_HW_H_</a></td></tr>
<tr class="memdesc:a612711f22572fe8a9b8622ccab1bac10"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#a612711f22572fe8a9b8622ccab1bac10">More...</a><br/></td></tr>
<tr class="separator:a612711f22572fe8a9b8622ccab1bac10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:af6c25057f14905b94ec9e1ec4b8a08f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sditx__hw_8h.html#af6c25057f14905b94ec9e1ec4b8a08f0">XV_SdiTx_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:af6c25057f14905b94ec9e1ec4b8a08f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="#af6c25057f14905b94ec9e1ec4b8a08f0">More...</a><br/></td></tr>
<tr class="separator:af6c25057f14905b94ec9e1ec4b8a08f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf4174bc728b414eb847050551b0ead9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sditx__hw_8h.html#adf4174bc728b414eb847050551b0ead9">XV_SdiTx_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:adf4174bc728b414eb847050551b0ead9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="#adf4174bc728b414eb847050551b0ead9">More...</a><br/></td></tr>
<tr class="separator:adf4174bc728b414eb847050551b0ead9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a473ff53a4f74d89a57e04a65c72416af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sditx__hw_8h.html#a473ff53a4f74d89a57e04a65c72416af">XV_SdiTx_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="xv__sditx__hw_8h.html#af6c25057f14905b94ec9e1ec4b8a08f0">XV_SdiTx_In32</a>((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:a473ff53a4f74d89a57e04a65c72416af"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a SDI TX register.  <a href="#a473ff53a4f74d89a57e04a65c72416af">More...</a><br/></td></tr>
<tr class="separator:a473ff53a4f74d89a57e04a65c72416af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a97b4db43e94f9ed2d5ef407db6607d59"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__sditx__hw_8h.html#a97b4db43e94f9ed2d5ef407db6607d59">XV_SdiTx_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="xv__sditx__hw_8h.html#adf4174bc728b414eb847050551b0ead9">XV_SdiTx_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:a97b4db43e94f9ed2d5ef407db6607d59"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a SDI TX register.  <a href="#a97b4db43e94f9ed2d5ef407db6607d59">More...</a><br/></td></tr>
<tr class="separator:a97b4db43e94f9ed2d5ef407db6607d59"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a612711f22572fe8a9b8622ccab1bac10"></a>
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          <td class="memname">#define XV_SDITX_HW_H_</td>
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<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="af6c25057f14905b94ec9e1ec4b8a08f0"></a>
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          <td class="memname">#define XV_SdiTx_In32&#160;&#160;&#160;Xil_In32</td>
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<p>Input Operations. </p>

</div>
</div>
<a class="anchor" id="adf4174bc728b414eb847050551b0ead9"></a>
<div class="memitem">
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          <td class="memname">#define XV_SdiTx_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output Operations. </p>

</div>
</div>
<a class="anchor" id="a473ff53a4f74d89a57e04a65c72416af"></a>
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          <td class="memname">#define XV_SdiTx_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__sditx__hw_8h.html#af6c25057f14905b94ec9e1ec4b8a08f0">XV_SdiTx_In32</a>((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads a value from a SDI TX register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the SDI TX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__sditx__hw_8h.html#a473ff53a4f74d89a57e04a65c72416af" title="This macro reads a value from a SDI TX register. ">XV_SdiTx_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__sditx_8h.html#a6449cab01d7b800c6b8f01bf8bb81836">XV_SdiTx_Axi4sBridgeVtcDisable()</a>, <a class="el" href="xv__sditx_8h.html#a8e8af66998e9542ee38de14c64ede3ef">XV_SdiTx_Axi4sBridgeVtcEnable()</a>, <a class="el" href="xv__sditx_8h.html#a97f7b4d5e3af35149bc9880e18ed26ed">XV_SdiTx_ClearDetectedError()</a>, <a class="el" href="xv__sditx_8h.html#a83c0ffc2e7ff9fe6c428dc6894bcc7fd">XV_SdiTx_ClearYCbCr444_RGB_10bit()</a>, <a class="el" href="xv__sditx_8h.html#a10230ff75d66b2ce63cc987ccb288d06">XV_SdiTx_DebugInfo()</a>, <a class="el" href="xv__sditx__intr_8c.html#a30aed08a4cb662a5dfff259fb1d19cac">XV_SdiTx_GetIntrEnable()</a>, <a class="el" href="xv__sditx__intr_8c.html#a8aa49027fc7d150a24c4745163a68459">XV_SdiTx_GetIntrStatus()</a>, <a class="el" href="xv__sditx__intr_8c.html#a1d6e97e9d2156a5f642e79a61e7d739f">XV_SdiTx_InterruptClear()</a>, <a class="el" href="xv__sditx__intr_8c.html#aa86b7cdd889edbe4395625a997b170ad">XV_SdiTx_IntrEnable()</a>, <a class="el" href="xv__sditx__intr_8c.html#a4d14ab6a4bf9dfcdc623126a17ba5275">XV_SdiTx_IntrHandler()</a>, <a class="el" href="xv__sditx_8h.html#aee1111d7059109893a1d72030ad1a9ac">XV_SdiTx_ReportDetectedError()</a>, <a class="el" href="group__v__sditx.html#gae535cd30cd5fd6414bf89142bc937e4a">XV_SdiTx_SelfTest()</a>, <a class="el" href="xv__sditx_8h.html#a62c8fbdcb856eff73bbb32ebcf78a41e">XV_SdiTx_SetColorFormat()</a>, <a class="el" href="xv__sditx_8h.html#a5ea8e0af6e69e9fc3376d880c3b01cdd">XV_SdiTx_SetCoreSettings()</a>, <a class="el" href="xv__sditx_8h.html#aa37349324994a3c15641e3dbd621ad2d">XV_SdiTx_SetPayloadLineNum()</a>, <a class="el" href="xv__sditx_8h.html#a46de41a6552e21e68a735b30a40d5044">XV_SdiTx_SetVidBridgeMode()</a>, <a class="el" href="xv__sditx_8h.html#a8907423180d202770dbdeb89cf94f0a9">XV_SdiTx_SetYCbCr444_RGB_10bit()</a>, <a class="el" href="xv__sditx_8h.html#ac68a902fd4b2c666020356621c33700d">XV_SdiTx_ST352CStreamEnable()</a>, <a class="el" href="xv__sditx_8h.html#afd56b720f4019c4a47715a803eb24bc3">XV_SdiTx_ST352CSwitch3GA()</a>, <a class="el" href="xv__sditx_8h.html#aac2a887b9e8db796240c9018c311f2ab">XV_SdiTx_StartSdi()</a>, <a class="el" href="xv__sditx_8h.html#a3bb43320e53ea983eb94f8e020ac1606">XV_SdiTx_StopSdi()</a>, <a class="el" href="xv__sditx_8h.html#a8ad731d07be9932825ca0ef037ae2299">XV_SdiTx_StreamStart()</a>, <a class="el" href="xv__sditx_8h.html#ae4d1cf84fcc0d5af0d704ad5e19485ab">XV_SdiTx_VidBridgeDisable()</a>, and <a class="el" href="xv__sditx_8h.html#adb4de6395b66aedaf45726f35181e0b8">XV_SdiTx_VidBridgeEnable()</a>.</p>

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          <td class="memname">#define XV_SdiTx_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__sditx__hw_8h.html#adf4174bc728b414eb847050551b0ead9">XV_SdiTx_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes a value to a SDI TX register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the SDI TX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__sditx__hw_8h.html#a97b4db43e94f9ed2d5ef407db6607d59" title="This macro writes a value to a SDI TX register. ">XV_SdiTx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__sditx_8h.html#a6449cab01d7b800c6b8f01bf8bb81836">XV_SdiTx_Axi4sBridgeVtcDisable()</a>, <a class="el" href="xv__sditx_8h.html#a8e8af66998e9542ee38de14c64ede3ef">XV_SdiTx_Axi4sBridgeVtcEnable()</a>, <a class="el" href="xv__sditx_8h.html#a97f7b4d5e3af35149bc9880e18ed26ed">XV_SdiTx_ClearDetectedError()</a>, <a class="el" href="xv__sditx_8h.html#a83c0ffc2e7ff9fe6c428dc6894bcc7fd">XV_SdiTx_ClearYCbCr444_RGB_10bit()</a>, <a class="el" href="xv__sditx__intr_8c.html#a1d6e97e9d2156a5f642e79a61e7d739f">XV_SdiTx_InterruptClear()</a>, <a class="el" href="xv__sditx__intr_8c.html#a3a6f57a2f45767bc0c0954adfe52c594">XV_SdiTx_IntrDisable()</a>, <a class="el" href="xv__sditx__intr_8c.html#aa86b7cdd889edbe4395625a997b170ad">XV_SdiTx_IntrEnable()</a>, <a class="el" href="xv__sditx_8h.html#a62c8fbdcb856eff73bbb32ebcf78a41e">XV_SdiTx_SetColorFormat()</a>, <a class="el" href="xv__sditx_8h.html#a5ea8e0af6e69e9fc3376d880c3b01cdd">XV_SdiTx_SetCoreSettings()</a>, <a class="el" href="xv__sditx_8h.html#acda96db01dd02a1a0f9142c10d177036">XV_SdiTx_SetPayloadId()</a>, <a class="el" href="xv__sditx_8h.html#aa37349324994a3c15641e3dbd621ad2d">XV_SdiTx_SetPayloadLineNum()</a>, <a class="el" href="xv__sditx_8h.html#a46de41a6552e21e68a735b30a40d5044">XV_SdiTx_SetVidBridgeMode()</a>, <a class="el" href="xv__sditx_8h.html#a8907423180d202770dbdeb89cf94f0a9">XV_SdiTx_SetYCbCr444_RGB_10bit()</a>, <a class="el" href="xv__sditx_8h.html#ac68a902fd4b2c666020356621c33700d">XV_SdiTx_ST352CStreamEnable()</a>, <a class="el" href="xv__sditx_8h.html#afd56b720f4019c4a47715a803eb24bc3">XV_SdiTx_ST352CSwitch3GA()</a>, <a class="el" href="xv__sditx_8h.html#aac2a887b9e8db796240c9018c311f2ab">XV_SdiTx_StartSdi()</a>, <a class="el" href="xv__sditx_8h.html#a3bb43320e53ea983eb94f8e020ac1606">XV_SdiTx_StopSdi()</a>, <a class="el" href="xv__sditx_8h.html#ae4d1cf84fcc0d5af0d704ad5e19485ab">XV_SdiTx_VidBridgeDisable()</a>, and <a class="el" href="xv__sditx_8h.html#adb4de6395b66aedaf45726f35181e0b8">XV_SdiTx_VidBridgeEnable()</a>.</p>

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